09. Exceptions and traps

What is «system event»?

Event type

Code position

Sure

Source

Name

Unexpected situation during execution: zero division, illegal instruction, illegal address etc.

Fixed

No

Internal

exception

Simulation of unexpected situation: «nothing happens, but we want to call a handler»

Fixed

Yes

Internal

trap

Expected situation handled by operating system (calling a certain system subroutine outside program code)

Fixed

Yes

Internal

syscall

Device request (like status change, I/O operation result, timer etc.)

Random

No

External

interrupt

Fatal device malfunction (bad media, system failure etc.)

Sometimes predictable

No

External

interrupt

Implementation:

Hardware requirements:

MIPS: exceptions

Exceptions, events and traps are handled by control CPU CPU0.

MARS: only partial support:

Name

Number

Purpose

BadVAddr

8

Address caused exception (if exception is related to incorrect memory addressing)

Status

12

Flags bit scale (interrupt mask, permissions etc.)

Cause

13

Event type and delayed event info

EPC

14

Address of instruction caused the exception or being executed when interrupt occurred

Instructions:

  1. mfc0 Rdest, C0src — move from C0 register C0src to common register Rdest

  2. mtc0 Rsrc C0des — move to C0

  3. eret — return from exception

Exception handling:

  1. Set up bit 1 of C0 $12 Status register (EXception Level, EXL).
  2. Set up bits 2-6 of C0 $13 Cause to exception type
  3. Store current instruction address to C0 $14 EPC
  4. If invalid addressing took place, set C0 $8 BadVAddr to accused memory address
  5. Jump to 0x8000180 (this address is fixed for MIPS32). The .ktext section (kernel code) is started from 0x8000000, so on real MIPS some instructions can be executed only from that part of memory.

  6. Handler must call eret after processing. This jumps to address stored at $14 (EPC) and cleans EXL status bit in $12.

    • When handling exception it's good idea to add 4 to EPC, so exception won't occur again

Real MIPS hardware and accurate simulators always have something in kernel space, but MARS has nothing and handles all exceptions/syscalls by executing Java code.

The Status C0 register (slightly MARS-specific):

bits

31-16

15-8

7-5

4

3-2

1

0

target

unused

Int. mask

unused

K/U

unused

Exception level

Int enable

The Cause C0 register

bits

31

30-16

15-8

7

6-2

1-0

target

Br

unused

Pending interrupts

unused

Exception code

unused

Exception handler

Exception types (partially in MARS):

Registers: handler can use $k0 and $k1 registers only, and must keep all other registers intact. Nothing should be changed after eret.

Simple example (debug it step by step):

   1 .text
   2         nop
   3         lw    $t0, ($zero)      # illegal read from 0x00000000
   4         li    $v0 10
   5         syscall
   6 
   7 .ktext  0x80000180
   8         mfc0    $k0 $14         # EPC keeps address of accused instruction
   9                                 # See also BadVAddr
  10         addi    $k0 $k0,4       # Next instruction is at EPC+4
  11         mtc0    $k0 $14         # Store that to EPС
  12         eret                    # Continue normal execution

Our more thorough handler must keep all registers intact, except for $k0 and $k1.

   1 .text
   2         lui     $t0 0x7fff
   3         addi    $t0 $t0 0xffff
   4         addi    $t0 $t0 0xffff  # integer overflow
   5         sw      $t0 0x400       # bad addressing
   6         divu    $t0 $t0 $zero   # zero division
   7         teq     $zero $zero     # trap (exception simulation)
   8         li      $v0 10
   9         syscall
  10 .kdata
  11 msg:    .asciiz "Exception "
  12 .ktext  0x80000180
  13         move    $k0 $v0         # keep $v0
  14         move    $k1 $a0         # keep $a0
  15         la      $a0 msg         # print a message
  16         li      $v0 4
  17         syscall
  18         mfc0    $a0 $13         # take Cause
  19         srl     $a0 $a0 2       # shift to cause number
  20         andi    $a0 $a0 0x1f    # separate it from other bits
  21         li      $v0 1           # print cause
  22         syscall
  23         li      $a0 10
  24         li      $v0 11          # print '\n'
  25         syscall
  26 
  27         move    $v0 $k0         # restore $v0
  28         move    $a0 $k1         # restore $a0
  29 
  30         li      $k0 0
  31         mtc0    $k0 $13         # clean Cause
  32         mfc0    $k0 $14         # take current instruction address from EPC
  33         addi    $k0 $k0,4       # calculate next instruction address
  34         mtc0    $k0 $14         # store back to EPС
  35         eret                    # let the program continue

Q: what common register we've corrupted anyway?

Note:

MIPS: traps

MIPS system event handling is fast an furious, so programmer may want to take advantage of it, developing new exceptions manually.

Trap is exception 13 and handles like all exceptions.

teq $t1,$t2

Trap if equal

Trap if $t1 is equal to $t2

teqi $t1,-100

Trap if equal to immediate

Trap if $t1 is equal to sign-extended 16 bit immediate

tge $t1,$t2

Trap if greater or equal

Trap if $t1 is greater than or equal to $t2

tgei $t1,-100

Trap if greater than or equal to immediate

Trap if $t1 greater than or equal to sign-extended 16 bit immediate

tgeiu $t1,-100

Trap if greater or equal to immediate unsigned

Trap if $t1 greater than or equal to sign-extended 16 bit immediate, unsigned comparison

tgeu $t1,$t2

Trap if greater or equal unsigned

Trap if $t1 is greater than or equal to $t2 using unsigned comparision

tlt $t1,$t2

Trap if less than

Trap if $t1 less than $t2

tlti $t1,-100

Trap if less than immediate

Trap if $t1 less than sign-extended 16-bit immediate

tltiu $t1,-100

Trap if less than immediate unsigned

Trap if $t1 less than sign-extended 16-bit immediate, unsigned comparison

tltu $t1,$t2

Trap if less than unsigned

Trap if $t1 less than $t2, unsigned comparison

tne $t1,$t2

Trap if not equal

Trap if $t1 is not equal to $t2

tnei $t1,-100

Trap if not equal to immediate

Trap if $t1 is not equal to sign-extended 16 bit immediate

Note these are atomic operations!

When trap is emitted, exception handler detects type 13 (trap) and can perform different actions based on EPC value (we know every trap address for sure).

R-type trap instruction can bear additional information at third register parameter field (dst). Handler can extract this data by reading and parsing word with the instruction, taken from address stored in EPC. But MARS assembler has no such feature.

Where to use:

H/W

HSE/ArchitectureASM/09_ExceptionsTraps (последним исправлял пользователь FrBrGeorge 2019-12-15 12:13:20)